Present day ultra-large-scale integration (ULSI) circuits may include hundreds of thousands or millions of interconnected active electronic devices on an integrated circuit chip. The large capital investment required to fabricate and test large scale integrated circuits prior to sale to a customer and the difficulty, expense and loss of goodwill associated with reworking and replacing integrated circuits which fail to operate as planned, have increased the need to accurately characterize the electrical behavior of integrated circuits prior to their manufacture.
Moreover, now that submicron and deep-submicron (0.5 .mu.m and below) technologies have begun to dominate silicon chip manufacturing and the prospect of million-plus-gate chips operating at clock rates of 100 MHz has become a reality, fundamental changes have had to be made to conventional integrated circuit design methodologies and the electronic design automation (EDA) tools based thereon. To meet these challenges, more sophisticated techniques for estimating electronic design parameters such as signal delay and power dissipation are required. In particular, accurate delay estimation now generally requires a stronger link between front-end tools such as chip partitioning and behavioral synthesis and back-end tools such as block placement and layout. Without such a link, deep-submicron designs may have to undergo multiple design iterations to meet specifications. This process can be expensive and time consuming. As illustrated by FIG. 1A, the number of layout iterations needed to eliminate timing violations generally increases significantly as logic density and clock speed increase. FIG. 1A also illustrates that more accurate delay estimation during front-end design generally leads to fewer time-consuming layout iterations. This saves money and shortens the design cycle. The data of FIG. 1A is based on a 0.8 .mu.m design having less than 30% of the chip die consumed by a large functional block and is a reproduction of FIG. 1 from an article by J. Lipman entitled Submicron EDA to Help Tackle Tough Designs, Electronic Design News, pp. 45-50, Jun. 8, 1995.
Unfortunately, as the minimum feature sizes of integrated circuits continue to shrink and operating speeds increase, characterization of the parasitic effects associated with passive nets (e.g., wiring) which interconnect the active devices within the circuit also may become more critical and more difficult. In the past, the effect of interconnect nets could generally be disregarded when simulating the operation of an integrated circuit, because the active devices therein typically dominated the overall circuit delay calculations while the delays associated with interconnect nets were typically considered negligible. However, as the minimum feature sizes of integrated circuits continue to shrink and the improvement in transistor propagation delay has exceeded that due to interconnect, the ratio of interconnect net delay to total delay has increased to greater than fifty percent (50%), as illustrated by FIG. 1B. In particular, as the minimum feature sizes decrease, the resistance and the height/width aspect ratio of the interconnect nets tend to increase and the number of wiring levels also typically tends to increase. The increased height/width aspect ratio and the close proximity of metal wiring lines at multiple levels makes cross-talk capacitance larger between adjacent wiring lines and makes the modeling of capacitance a three-dimensional problem instead of a two-dimensional problem. Now, interconnects generally can no longer be simply modeled as equivalent to a single resistor and capacitor--a lumped equivalent circuit. Instead, EDA tools that predict interconnect delay or extract wiring parasitics for back annotation into the circuit typically use distributed RC equivalent networks to model the interconnects. Accordingly, a complete analysis of the behavior of state-of-the-art integrated circuits typically must account for the resistive and capacitive effects of the interconnect paths in addition to the active devices.
However, because detailed extraction of the resistance and capacitance of the nets is typically required to accurately model total interconnect delay and because complex three-dimensional capacitance models are typically required to extract accurate capacitance values, a complete characterization of the active devices and interconnect nets can become extremely time consuming and may exceed the storage capabilities of the processing system on which the characterization is being performed. Thus, attempts to account for timing delays associated with interconnect nets by performing extraction have typically been limited to only certain sections or blocks of a design and have typically used simplified extraction models to improve runtime.
Attempts have also been made to reduce the complexity of extraction by applying heuristic approaches, such as by selecting only clock nets, "top level" nets, nets with large total capacitance or nets within preselected timing critical paths determined by simplified simulation techniques. For example, traditional attempts to account for the timing delays associated with interconnect nets typically include the steps of performing detailed extraction only after timing critical paths have already been determined. As illustrated best by FIG. 2, such attempts include the steps of supplementing a circuit netlist with unbounded parasitic estimates of the resistance and capacitance of the interconnect nets and then performing a timing simulation of the circuit to identify potential timing critical paths. Detailed parasitic extraction of those nets in the timing critical paths may then be performed to determine an updated estimate of the delay associated with the timing critical paths. Unfortunately, these and related attempts typically rely on relatively inaccurate parasitic estimates based on simplified models which can cause the timing analysis tool to select "false" critical paths and miss "real" critical paths. This means that necessary detailed parasitic extraction may not be performed on some layout critical nets.
Other traditional approaches include the net constraint and path constraint approach. In the net constraint approach, a user specifies fixed net constraint values across a design to guide a layout program. One of the drawbacks of this approach is the difficulty of sharing timing resources among several nets. A timing resource is a portion of an overall delay to be distributed through a physical layout. In addition, this approach may fail to account for the fact that different paths usually share common nets. Thus, a burden is placed on a designer to divide path delays into net delays, before the actual layout of the nets has actually been determined. This approach is also limited by the fact that net delay constraints are generally fixed and typically cannot be altered during layout. In the case where one of the nets in a path takes up a shorter than expected delay, it may be difficult to share this extra timing resource with other nets in the same path in the event their respective net delay constraints are underestimated. Finally, in the path constraint approach, the whole path is constrained to meet a target path delay. But, because the relationships between different timing paths can be complicated, even a slight movement of a cell during layout can significantly affect the delays of many nets. This, in turn, can require a reevaluation of the delays on numerous paths. Due to these drawbacks, designers commonly only constrain a few of what they think will likely be the most timing critical paths which means that real timing critical paths may be missed.
Thus, notwithstanding the above described methods of accounting for timing delays associated with interconnect nets by evaluating only certain blocks of a circuit design, using simplified models and/or applying heuristic approaches, there continues to be a need for improved methods and apparatus for taking into account interconnect delays when simulating microelectronic circuits and evaluating their performance.